Field of the Invention
The present invention relates to cascode structures and particularly to dual-gate transistors having an insulating layer below one gate. The present invention also relates to transistors including a field plate and particularly to transistors having a field plate relatively near the semiconductor layers.
Description of the Related Art
Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for low power and, in the case of Si, low frequency applications. However, these more familiar semiconductor materials may not be well-suited for high power and/or high frequency applications, for example, due to their relatively small bandgaps (1.12 eV for Si and 1.42 for GaAs at room temperature) and relatively small breakdown voltages.
In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and/or high frequency applications and devices has focused on wide bandgap semiconductor materials such as silicon carbide (2.996 eV for alpha SiC at room temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials, typically, may have higher electric field breakdown strengths and higher electron saturation velocities as compared to GaAs and Si.
A device of particular interest for high power and/or high frequency applications is the High Electron Mobility Transistor (HEMT), which is also known as a modulation doped field effect transistor (MODFET). In a HEMT device, a two-dimensional electron gas (2DEG) may be formed at the heterojunction of two semiconductor materials with different bandgap energies. The smaller bandgap material may have a higher electron affinity than the wider bandgap material. The 2DEG is an accumulation layer in the undoped smaller bandgap material and can contain a relatively high sheet electron concentration, for example, in excess of 1013 carriers/cm2. Additionally, electrons that originate in the wider bandgap semiconductor may transfer to the 2DEG, allowing a relatively high electron mobility due to reduced ionized impurity scattering. This combination of relatively high carrier concentration and carrier mobility can give the HEMT a relatively large transconductance and may provide a performance advantage over metal-semiconductor field effect transistors (MESFETS) for high-frequency applications.
HEMTs fabricated in the gallium nitride/aluminum gallium nitride (GaN/AlGaN) material system can generate large amounts of RF power due to a combination of material characteristics, such as relatively high breakdown fields, relatively wide bandgaps, relatively large conduction band offset, and/or relatively high saturated electron drift velocity. A major portion of the electrons in the 2DEG may be attributed to polarization in the AlGaN.
Different types of HEMTs in the GaN/AlGaN system have been demonstrated. For example, U.S. Pat. Nos. 5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methods of manufacture. In addition, U.S. Pat. No. 6,316,793, to Sheppard et al., which is commonly assigned with the present application, describes a HEMT device having a semi-insulating silicon carbide substrate, an AlN buffer layer on the substrate, an insulating GaN layer on the buffer layer, an AlGaN barrier layer on the GaN layer, and a passivation layer on the AlGaN active structure. Moreover, U.S. Patent Application Publication No. U.S. 2005/0170574 to Sheppard et al., which is also commonly assigned, describes a HEMT device including a protective layer and/or a low damage recess fabrication technique which may reduce damage to the semiconductor in the gate region of the transistor that can occur during an anneal of the ohmic contacts of the device.
Electron trapping and the resulting difference between DC and RF characteristics can be a limiting factor in the performance of these devices. Silicon nitride (SiN) passivation has been employed to alleviate this trapping problem resulting in high performance devices with power densities over 10 W/mm at 10 Ghz. For example, commonly assigned U.S. Pat. No. 6,586,781 to Wu et al. discloses methods and structures for reducing the trapping effect in GaN-based transistors. However, due to the high electric fields existing in these structures, charge trapping can still be a concern.
Field plates have been used to enhance the performance of GaN-based HEMTs at microwave frequencies and have exhibited performance improvement over non-field-plated devices [See S. Kamalkar and U. K. Mishra, Very High Voltage AlGaN/GaN High Electron Mobility Transistors Using a Field Plate Deposited on a Stepped Insulator, Solid State Electronics 45, (2001), pp. 1645-1662]. Many field plate approaches have involved a field plate connected to the gate of the transistor with the field plate on top of the drain side of a channel. This can result in a reduction of the electric field on the gate-to-drain side of the transistor, thereby increasing breakdown voltage and reducing the high-field trapping effect. However, transistors with gate-to-drain field plates can exhibit relatively poor reliability performance, particularly at class C (or higher class) operation where the electric field on the source side of the gate becomes significant.
It is well known that field plate approaches involving connecting the field plate to the source offer a reduction in gate-to-drain capacitance Cgd, which consequently can enhance the gain. In addition to minimizing capacitance, one goal in some applications is to improve linearity (i.e., the degree of proportionality between input and output) and reduce the drain bias dependence of the capacitance. While GaN-based HEMTs generally display good linearity, in some applications further improvement is desired (e.g., high power RF or and/or communication applications).
FIG. 1A shows a prior art transistor 10 having a field plate 28 connected to a source 22. The transistor 10 also includes a gate 26 which is on a barrier layer 18 and arranged between the source 22 and a drain 24, and within an insulating spacer layer 21. The barrier layer 18 is on a layer sequence including a 2DEG 20, a buffer layer 16, and a substrate 12. FIG. 1B is a chart showing the capacitance Cgd as a function of drain voltage Vd for a structure similar to the transistor 10. While this structure can have a reduced capacitance Cgd compared to structures without a field plate, the capacitance Cgd can still show a large dependence on the bias of the drain 24 as shown by FIG. 1B and shows a linearity with room for improvement.
One method of minimizing feedback capacitance while also improving linearity involves multi-stage arrangements. Transistors such as HEMTs can be combined in a two-stage cascade arrangement (using two of the same or different transistors). Some cascode arrangements including an initial non-field-plated common source stage and a second field-plated common gate stage are described in the commonly assigned U.S. Pat. No. 7,126,426 to Mishra et al. and entitled “Cascode Amplifier Structure Including Wide Bandgap Field Effect Transistor With Field Plates,” which is fully incorporated by reference herein in its entirety. These devices can obtain the benefits of the field plate with little detrimental impact due to the feedback capacitance caused by the use of the field plate.
Multi-stage arrangements can also be achieved within a single dual-gate transistor, such as those described in U.S. Pat. No. 5,514,992 to Tanaka et al. In a dual-gate cascode transistor, the drain-to-source connection of a two transistor arrangement is replaced by the portion of the transistor between the two gates. FIG. 1C shows a prior art HEMT 11 with a dual-gate cascode arrangement including many of the same elements as the transistor 10 (like reference numerals are used to indicate like elements). The HEMT 11 includes a first stage gate 26 and a second stage gate 29 which are on the barrier layer 18 and arranged between the source 22 and drain 24. The second gate 29 can act as a shield for the first gate 26, and thus can reduce the feedback capacitance between the first gate 26 and drain 24, can reduce the drain voltage dependence of the capacitance, and can improve linearity.
In prior art dual-gate arrangements such as that shown in FIG. 1C, the first and second stages have the same threshold voltage. If the second gate in such an arrangement is grounded, then the current flow can be limited. Because of this, the second stage must be DC biased so as to avoid limiting the maximum current of the device. Some such devices are described in U.S. Pub. No. 2007/0290762 to Lin et al. However, separately biasing the second stage leads to added complexity and cost.